1. Field of the Invention
The present invention relates to signal processing and more particularly to mechanizing finite (.ltoreq.N TAP) impulse response filters using N-point fast-Fourier transformations and fast convolution. The invention further relates to a multiplier structure for use in a real-only data fast convolution filter with a minimum number of multiplication elements.
2. Related Technical Art
Finite impulse response filters are used extensively in many advanced signal-processing applications for signal equalization, adaptive filtering, contouring, and improving signal-to-noise ratios. Modern digital signal processing has advanced the applicability of FIR filters through the use of fast convolution and fast-Fourier transformation techniques, each of which reduce overall filter size and provide high speed high transfer rate digital implementations.
However, aside from speed and data-throughput requirements, system complexity and size are still major concerns for many filter implementations. Larger or more complex filters are often harder to manufacture and consume too much power for many applications. Increased system complexity also requires increased numbers of computational elements to mechanize a given function, both in terms of hardware and software. Therefore, highly complex or computational intensive algorithms and processing designs demand more circuitry or computational elements and, often, larger circuit memory to implement, either of which is undesirable in many applications. Unfortunately, the filter accuracy demanded in many advanced technology applications also requires very long or more complex filter structures.
The typical approach to fast convolution FIR filter mechanization relies on certain conventional or traditional methods of complex frequency data multiplication in the transition between fast-Fourier transform (FFT) data and inverse-fast-Fourier transform (IFFT) data, or between frequency and time domain data during the filtering process. The number of real multiplications per input data point dictated by these techniques is relatively high and translates to an excessive number of multiplication elements in the filter apparatus. The number of multiplications or multipliers needed for FIR filtering with 128 (or more) coefficients, even with known circuit reduction techniques can consume a large amount of apparatus area or software memory to accommodate.
What is needed, then, is a method of maximizing computational performance and providing the equivalent of very long FIR filter structures, while minimizing the amount of circuitry required to perform frequency domain multiplications. It is also desirable to implement the filter processing functions in a compact architecture which utilizes well understood manufacturing technology and is inexpensive to implement. A flexible structure capable of dynamically changing multiplicative factors based on specific application requirements would also be useful.